module test_7044clk (
    input  clk_27dr_p        ,   
    input  clk_27dr_n        ,
    output clk_27dr          ,
    output clk_491p52        ,
    output clk_245p76        ,
    input  reg_reset         ,
    output clk_inst_locked
);

    wire clk_27dr_ibufds;
    wire clk_27dr_491p52;
    wire clk_27dr_245p76;

    BUFG clk_bufg (
        .O(clk_27dr),        // 1-bit output: Clock output
        .I(clk_27dr_ibufds)  // 1-bit input: Clock input
    );

    IBUFDS clk_ibufds (
        .O(clk_27dr_ibufds),   // 1-bit output: Buffer output
        .I(clk_27dr_p),        // 1-bit input: Diff_p buffer input (connect directly to top-level port)
        .IB(clk_27dr_n)        // 1-bit input: Diff_n buffer input (connect directly to top-level port)
    );

    BUFG clk_adc_bufg (
      .O(clk_491p52), 
      .I(clk_27dr_491p52) 
    );

    BUFG clk_dac_bufg (
      .O(clk_245p76), 
      .I(clk_27dr_491p52) 
    );

    clk_from_7044 clk_27dr_inst 
    (
        .clk_out1  (clk_27dr_491p52)      , 
        .clk_out2  (clk_27dr_245p76)      , 
        .reset     (reg_reset)            , 
        .locked    (clk_inst_locked)      , 
        .clk_in1   (clk_27dr)
    );

//   output clk_out1;
//   output clk_out2;
//   input reset;
//   output locked;
//   input clk_in1;

endmodule